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» Formal Models for Embedded System Design
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FMICS
2009
Springer
14 years 3 months ago
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
Matthias Raffelsieper, Mohammad Reza Mousavi, Jan-...
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
14 years 1 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
FPL
2007
Springer
133views Hardware» more  FPL 2007»
14 years 3 months ago
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guille...
DATE
2003
IEEE
116views Hardware» more  DATE 2003»
14 years 2 months ago
Development and Application of Design Transformations in ForSyDe
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstractio...
Ingo Sander, Axel Jantsch, Zhonghai Lu
ICFEM
2003
Springer
14 years 2 months ago
Formalization, Testing and Execution of a Use Case Diagram
Abstract. Errors in a requirements model have prolonged detrimental effects on reliability, cost, and safety of a software system. It is very costly to fix these errors in later ...
Wuwei Shen, Shaoying Liu