726 search results - page 11 / 146 » Formal Verification and Validation of Interactive Systems Sp... |
MICRO
2008
IEEE
13 years 8 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
DEXAW
1999
IEEE
14 years 23 days ago
1999
IEEE
The wide variety of abstract system development methodologies available includes the waterfall and V models. These models are often too generic and need careful adaptation to suit ...
FDL
2007
IEEE
14 years 2 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
FMCAD
2000
Springer
14 years 1 days ago
2000
Springer
Abstract. In this paper we describe the formal specification and verification of the efficient algorithm for real-time model checking implemented in the model checker RAVEN. It was...
ENTCS
2008
13 years 8 months ago
2008
This paper presents our solutions to some problems we encountered in an ongoing attempt to verify the micro-hypervisor currently developed within the Robin project. The problems t...