216 search results - page 17 / 44 » Formal Verification of Safety Properties in Timed Circuits |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
JSS
2010
13 years 6 months ago
2010
—Probabilistic properties are considered as the most important requirements for a variety of software systems, since they are used to formulate extra-functional requirements such...
ISORC
1998
IEEE
13 years 11 months ago
1998
IEEE
Many modern chemical plants have to be modelled as complex hybrid systems consisting of various continuous and event-discrete components. Besides of the modular and easy-to-read s...
FDL
2003
IEEE
14 years 26 days ago
2003
IEEE
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...