1446 search results - page 161 / 290 » Formal analysis of hardware requirements |
ISCAS
1999
IEEE
14 years 2 months ago
1999
IEEE
In a companion paper of this session [1] we formally defined the notion of equivalence classes of circuits which are physical clones of an existing benchmark seed circuit created ...
ASPDAC
1998
ACM
14 years 2 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
ACSD
2004
IEEE
14 years 2 months ago
2004
IEEE
Over the last 25 years, methods for supervisory control of discrete event systems and methods for submodule construction based on state machine specifications have been developed ...
DSD
2006
IEEE
14 years 2 months ago
2006
IEEE
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
CHARME
2005
Springer
14 years 11 days ago
2005
Springer
Abstract. Automatic formal verification techniques generally require exponential resources with respect to the number of primary inputs of a netlist. In this paper, we present sev...