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» Formal analysis of hardware requirements
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ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 1 months ago
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems
This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for applicationspecific systems, called VAbM technique. It targets th...
Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma,...
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
14 years 15 days ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
14 years 11 days ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
14 years 10 days ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
ASAP
1997
IEEE
144views Hardware» more  ASAP 1997»
14 years 9 days ago
Automatic data mapping of signal processing applications
This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applicati...
Corinne Ancourt, Denis Barthou, Christophe Guettie...