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» Formal analysis of hardware requirements
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CODES
2007
IEEE
14 years 2 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 1 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
IAAI
2003
13 years 9 months ago
A Cellular Telephone-Based Application for Skin-Grading to Support Cosmetic Sales
We have developed a sales support system for door-todoor sales of cosmetics based on a skin-image grading system called Skin-CRM (Skin Customer Relationship Management). Our Skin-...
Hironori Hiraishi, Fumio Mizoguchi
MLMI
2004
Springer
14 years 1 months ago
Towards Predicting Optimal Fusion Candidates: A Case Study on Biometric Authentication Tasks
Combining multiple information sources, typically from several data streams is a very promising approach, both in experiments and to some extend in various real-life applications. ...
Norman Poh, Samy Bengio
PEWASUN
2007
ACM
13 years 9 months ago
Worst-case lifetime computation of a wireless sensor network by model-checking
Wireless Sensor Network (WSN) technology is now mature enough to be used in numerous application domains. However, due to the restricted amount of energy usually allocated to each...
Laurent Mounier, Ludovic Samper, Wassim Znaidi