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» Formal testing from timed finite state machines
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FPL
2000
Springer
155views Hardware» more  FPL 2000»
13 years 11 months ago
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...
Valery Sklyarov
CONCUR
2000
Springer
13 years 11 months ago
Reachability Analysis for Some Models of Infinite-State Transition Systems
We introduce some new models of infinite-state transition systems. The basic model, called a (reversal-bounded) counter machine (CM), is a nondeterministic finite automaton augment...
Oscar H. Ibarra, Tevfik Bultan, Jianwen Su
QSIC
2003
IEEE
14 years 23 days ago
Validating Use-Cases with the AsmL Test Tool
The Abstract State Machine Language supports use-case oriented modeling in a faithful way. In this paper we discuss how the AsmL test tool, a new component of the AsmL tool environ...
Michael Barnett, Wolfgang Grieskamp, Wolfram Schul...
COLING
1992
13 years 8 months ago
Compiling and Using Finite-State Syntactic Rules
A language-independent framework for syntactic finlte-state parsing is discussed. The article presents a framework, a formalism, a compiler and a parser for grammars written in th...
Kimmo Koskenniemi, Pasi Tapanainen, Atro Voutilain...
ASE
2010
126views more  ASE 2010»
13 years 7 months ago
Generating a checking sequence with a minimum number of reset transitions
Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states t...
Robert M. Hierons, Hasan Ural