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» Formal verification of analog designs using MetiTarski
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DAC
2003
ACM
14 years 8 months ago
Support vector machines for analog circuit performance representation
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...
Fernando De Bernardinis, Michael I. Jordan, Albert...
IFIP
2010
Springer
13 years 2 months ago
A Formal Analysis of Authentication in the TPM
The Trusted Platform Module (TPM) is a hardware chip designed to enable computers to achieve a greater level of security than is possible in software alone. To this end, the TPM pr...
Stéphanie Delaune, Steve Kremer, Mark Dermo...
RTAS
1998
IEEE
13 years 11 months ago
Verification of the Fast Reservation Protocol with Delayed Transmission using the Tool Kronos
In this paper we report the work carried out at VERIMAG 1 within the framework of an research cooperation with CNET 2 . The goal of this work was twofold: to formally specify the ...
Stavros Tripakis, Sergio Yovine
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
14 years 1 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
POPL
2008
ACM
14 years 7 months ago
Formal verification of translation validators: a case study on instruction scheduling optimizations
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
Jean-Baptiste Tristan, Xavier Leroy