299 search results - page 20 / 60 » Formal verification of analog designs using MetiTarski |
FMCO
2008
Springer
13 years 9 months ago
2008
Springer
In this paper, we present a framework for formal modeling and verification of service-based business processes with focus on their compliance to external regulations such as Segreg...
EUROMICRO
2000
IEEE
13 years 12 months ago
2000
IEEE
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...