299 search results - page 9 / 60 » Formal verification of analog designs using MetiTarski |
ISICT
2003
13 years 8 months ago
2003
: Formal verification provides a rigid and thorough means of evaluating the correctness of cryptographic protocols so that even subtle defects can be identified. As the application...
ISARCS
2010
13 years 9 months ago
2010
Methods of formal description and verification represent a viable way for achieving fundamentally bug-free software. However, in reality only a small subset of the existing operati...
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
ISORC
2000
IEEE
13 years 11 months ago
2000
IEEE
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
WWW
2006
ACM
14 years 8 months ago
2006
ACM
The need of formal verification is a problem that involves all the fields in which sensible data are managed. In this context the verification of data streams became a fundamental...