202 search results - page 25 / 41 » Framework for Fault Analysis and Test Generation in DRAMs |
ITC
2002
IEEE
14 years 10 days ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
CCGRID
2009
IEEE
14 years 2 months ago
2009
IEEE
—Cloud computing has emerged as a new technology that provides large amount of computing and data storage capacity to its users with a promise of increased scalability, high avai...
KBSE
2009
IEEE
14 years 2 months ago
2009
IEEE
—We investigate claims and assumptions made in several recent papers about fault localization (FL) techniques. Most of these claims have to do with evaluating FL accuracy. Our in...
JSS
2007
13 years 7 months ago
2007
This paper describes an approach for generating customized benchmark suites from a software architecture description following a Model Driven Architecture (MDA) approach. The benc...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...