Hoare logic is bedevilled by complex but coarse side conditions on the use of variables. We define a logic, free of side conditions, which permits more precise statements of a pr...
Matthew J. Parkinson, Richard Bornat, Cristiano Ca...
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...
Abstract. In this paper we propose a novel technique for constructing timed automata from properties expressed in the logic MTL, under bounded-variability assumptions. We handle fu...
tract State Machines to Concurrent Transaction Logic Dumitru Roman1 , Michael Kifer2 , and Dieter Fensel1 1 STI Innsbruck, Austria 2 State University of New York at Stony Brook, US...
Soundness proofs of program logics such as Hoare logics and type systems are often made easier by decorating the operational semantics with information that is useful in the proof...