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TC
2008
13 years 8 months ago
RACE: A Robust Adaptive Caching Strategy for Buffer Cache
While many block replacement algorithms for buffer caches have been proposed to address the wellknown drawbacks of the LRU algorithm, they are not robust and cannot maintain a cons...
Yifeng Zhu, Hong Jiang
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout
ACL
2012
11 years 11 months ago
Building Trainable Taggers in a Web-based, UIMA-Supported NLP Workbench
Argo is a web-based NLP and text mining workbench with a convenient graphical user interface for designing and executing processing workflows of various complexity. The workbench...
Rafal Rak, BalaKrishna Kolluru, Sophia Ananiadou
DIAGRAMS
2006
Springer
14 years 16 days ago
Flow Diagrams: Rise and Fall of the First Software Engineering Notation
Drawings of water are the earliest, least abstract forms of flow diagram. Representations of ideal or generalised sequences for manufacturing or actual paths for materials between ...
Stephen J. Morris, O. C. Z. Gotel
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 2 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...