26 search results - page 4 / 6 » Full-Chip Multilevel Routing for Power and Signal Integrity |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
ICCAD
2009
IEEE
13 years 4 months ago
2009
IEEE
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
IJCNN
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time a...
GLVLSI
2005
IEEE
14 years 22 days ago
2005
IEEE
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today’s mixed signal system integration. In this wo...
ISCA
2009
IEEE
14 years 1 months ago
2009
IEEE
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...