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ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 27 days ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
ASPLOS
1989
ACM
13 years 11 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
ANCS
2010
ACM
13 years 5 months ago
DOS: a scalable optical switch for datacenters
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and highthroughput interconnections within a data center. DO...
Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent...
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 2 months ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...
SIGMETRICS
2005
ACM
120views Hardware» more  SIGMETRICS 2005»
14 years 1 months ago
Managing server energy and operational costs in hosting centers
The growing cost of tuning and managing computer systems is leading to out-sourcing of commercial services to hosting centers. These centers provision thousands of dense servers w...
Yiyu Chen, Amitayu Das, Wubi Qin, Anand Sivasubram...