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VTS
2000
IEEE
94views Hardware» more  VTS 2000»
14 years 1 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
ACMSE
2008
ACM
13 years 11 months ago
Optimization of the multiple retailer supply chain management problem
With stock surpluses and shortages representing one of the greatest elements of risk to wholesalers, a solution to the multiretailer supply chain management problem would result i...
Caio Soares, Gerry V. Dozier, Emmett Lodree, Jared...
BMCBI
2006
150views more  BMCBI 2006»
13 years 9 months ago
Predicting protein subcellular locations using hierarchical ensemble of Bayesian classifiers based on Markov chains
Background: The subcellular location of a protein is closely related to its function. It would be worthwhile to develop a method to predict the subcellular location for a given pr...
Alla Bulashevska, Roland Eils
BMCBI
2007
140views more  BMCBI 2007»
13 years 9 months ago
From genes to functional classes in the study of biological systems
Background: With the popularisation of high-throughput techniques, the need for procedures that help in the biological interpretation of results has increased enormously. Recently...
Fátima Al-Shahrour, Leonardo Arbiza, Hern&a...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 2 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng