192 search results - page 30 / 39 » Functional Scan Chain Testing |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
This paper describes an efficient implementation of an effective sequential synthesis operation that uses induction to detect and merge sequentially-equivalent nodes. State-encodi...
ASPDAC
2007
ACM
13 years 12 months ago
2007
ACM
- A Cyclic-CPRS (Column Parity Row Selection) technique is presented to diagnose built-in self tested (BISTed) circuits, even in the presence of many unknowns and transient errors....
BMCBI
2010
13 years 8 months ago
2010
Background: The impressive increase of novel RNA structures, during the past few years, demands automated methods for structure comparison. While many algorithms handle only small...
GLVLSI
1999
IEEE
14 years 5 days ago
1999
IEEE
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
TVLSI
2002
13 years 7 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...