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» Functional Test Generation for FSMs by Fault Extraction
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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
13 years 12 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
TCAD
2008
114views more  TCAD 2008»
13 years 7 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
ATS
2003
IEEE
151views Hardware» more  ATS 2003»
14 years 24 days ago
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
Junhao Shi, Görschwin Fey, Rolf Drechsler
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
13 years 11 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
ISESE
2002
IEEE
14 years 12 days ago
Elimination of Crucial Faults by a New Selective Testing Method
Recent software systems contain a lot of functions to provide various services. According to this tendency, software testing becomes more difficult than before and cost of testing...
Masayuki Hirayama, Tetsuya Yamamoto, Jiro Okayasu,...