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» Functional Test Generation for FSMs by Fault Extraction
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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 13 days ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
VTS
2008
IEEE
83views Hardware» more  VTS 2008»
14 years 1 months ago
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
Jeremy Lee, Mohammad Tehranipoor
ICTAI
2002
IEEE
14 years 12 days ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
ITC
1995
IEEE
104views Hardware» more  ITC 1995»
13 years 11 months ago
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
Nur A. Touba, Edward J. McCluskey
GI
2007
Springer
14 years 1 months ago
Automated Test Case Selection Based on a Similarity Function
: A strategy for automatic test case selection based on the use of a similarity function is presented. Test case selection is a crucial activity to model-based testing since the nu...
Emanuela G. Cartaxo, Francisco G. Oliveira Neto, P...