174 search results - page 21 / 35 » Functional Test Generation for Full Scan Circuits |
GLVLSI
2002
IEEE
14 years 3 months ago
2002
IEEE
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
TCAD
2008
13 years 10 months ago
2008
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
ICCAD
1995
IEEE
14 years 2 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
ATS
2003
IEEE
14 years 4 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
DAC
2001
ACM
14 years 11 months ago
2001
ACM
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...