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» Functional Test Generation for Full Scan Circuits
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VTS
2007
IEEE
100views Hardware» more  VTS 2007»
14 years 5 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
ITC
1989
IEEE
70views Hardware» more  ITC 1989»
14 years 2 months ago
The Pseudo-Exhaustive Test of Sequential Circuits
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
Sybille Hellebrand, Hans-Joachim Wunderlich
DAC
1994
ACM
14 years 2 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
DATE
2009
IEEE
90views Hardware» more  DATE 2009»
14 years 5 months ago
A scalable method for the generation of small test sets
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
Santiago Remersaro, Janusz Rajski, Sudhakar M. Red...
VTS
1999
IEEE
114views Hardware» more  VTS 1999»
14 years 3 months ago
Partial Scan Using Multi-Hop State Reachability Analysis
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
Sameer Sharma, Michael S. Hsiao