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EH
1999
IEEE
351views Hardware» more  EH 1999»
14 years 1 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
ENTCS
2006
113views more  ENTCS 2006»
13 years 8 months ago
Concurrent Java Test Generation as a Search Problem
A Random test generator generates executable tests together with their expected results. In the form of a noise-maker, it seeds the program with conditional scheduling primitives ...
Yaniv Eytani
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 5 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
DAC
2001
ACM
14 years 9 months ago
An Algorithm for Bi-Decomposition of Logic Functions
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
Alan Mishchenko, Bernd Steinbach, Marek A. Perkows...
TPHOL
2009
IEEE
14 years 3 months ago
Formalising FinFuns - Generating Code for Functions as Data from Isabelle/HOL
Abstract. FinFuns are total functions that are constant except for a finite set of points, i.e. a generalisation of finite maps. We formalise them in Isabelle/HOL and present how...
Andreas Lochbihler