82 search results - page 11 / 17 » Functional Testing of Microprocessors with Graded Fault Cove... |
TC
1998
13 years 7 months ago
1998
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
ICTAI
2002
IEEE
14 years 13 days ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead. A probabilistic analysis shows that the output of an LFSR which fee...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...