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IOLTS
2003
IEEE
126views Hardware» more  IOLTS 2003»
14 years 2 months ago
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...
POPL
2000
ACM
14 years 1 months ago
(Optimal) Duplication is not Elementary Recursive
In 1998 Asperti and Mairson proved that the cost of reducing a lambda-term using an optimal lambda-reducer (a la L´evy) cannot be bound by any elementary function in the number o...
Andrea Asperti, Paolo Coppola, Simone Martini
DAC
2010
ACM
14 years 25 days ago
Theoretical analysis of gate level information flow tracking
Understanding the flow of information is an important aspect in computer security. There has been a recent move towards tracking information in hardware and understanding the flow...
Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Tim...
FPL
2007
Springer
128views Hardware» more  FPL 2007»
14 years 3 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton
CF
2008
ACM
13 years 11 months ago
Exact combinational logic synthesis and non-standard circuit design
Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first ba...
Paul Tarau, Brenda Luderman