Sciweavers

2076 search results - page 157 / 416
» Functional logic overloading
Sort
View
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 3 months ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
LATIN
2004
Springer
14 years 3 months ago
A Proof System and a Decision Procedure for Equality Logic
Equality logic with or without uninterpreted functions is used for proving the equivalence or refinement between systems (hardware verification, compiler’s translation, etc). C...
Olga Tveretina, Hans Zantema
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
14 years 3 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
ASYNC
1998
IEEE
100views Hardware» more  ASYNC 1998»
14 years 2 months ago
An Implicit Method for Hazard-Free Two-Level Logic Minimization
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
Michael Theobald, Steven M. Nowick
ER
2007
Springer
167views Database» more  ER 2007»
14 years 2 months ago
An Unified Dynamic Description Logic Model for Databases: Relational Data, Relational Operations and Queries
The paper presents an unified Description Logic (DL) model for databases. Describing database models using DLs is a fundamental problem in many areas because it turns databases to...
Guoshun Hao, Shilong Ma, Yuefei Sui, Jianghua Lv