Technology Mapping for Reliability Enhancement in Logic Synthesis

Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliability is commonly ignored during the logic synthesis step. A major reason for this is the fact that constructing a cost function to measure sensitivity to faults at the logic synthesis level is complex. The work presented in this paper addresses one important aspect of synthesis for high reliability. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with Fault Sensitivity [3] as an optimization metric. We believe that the difficulty in obtaining accurate metrics of fault sensitivity at the technology independent level makes it hard to optimize at this level, thus technology dependent mapping offers a direct method to improve reliability. In this paper, we present a concept named “effective fault area” for mapping onto lib...

• Type: Conference
• Year: 2005
• Where: ISQED
• Authors: Zhaojun Wo, Israel Koren
• Keywords: Fault Sensitivity, Hardware, ISQED 2005, Logic Synthesis, Logic Synthesis Level