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» Functional logic overloading
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TCAD
2002
146views more  TCAD 2002»
13 years 8 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
14 years 2 months ago
Circular BIST testing the digital logic within a high speed Serdes
High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BIST for testing the digital part of a serdes using ci...
Graham Hetherington, Richard Simpson
ASPDAC
2007
ACM
80views Hardware» more  ASPDAC 2007»
14 years 22 days ago
Recognition of Fanout-free Functions
Factoring is a logic minimization technique to represent a Boolean function in an equivalent function with minimum literals. When realizing the circuit, a function represented in ...
Tsung-Lin Lee, Chun-Yao Wang
VMCAI
2010
Springer
14 years 6 months ago
Collections, Cardinalities, and Relations
Abstract. Logics that involve collections (sets, multisets), and cardinality constraints are useful for reasoning about unbounded data structures and concurrent processes. To make ...
Kuat Yessenov, Ruzica Piskac, Viktor Kuncak
ISMVL
2008
IEEE
160views Hardware» more  ISMVL 2008»
14 years 3 months ago
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean Sati...
Daniel Große, Robert Wille, Gerhard W. Dueck...