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DAC
1999
ACM
14 years 1 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
POPL
2012
ACM
12 years 4 months ago
Higher-order functional reactive programming in bounded space
Functional reactive programming (FRP) is an elegant and successful approach to programming reactive systems declaratively. The high levels of abstraction and expressivity that mak...
Neelakantan R. Krishnaswami, Nick Benton, Jan Hoff...
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ICCAD
2010
IEEE
156views Hardware» more  ICCAD 2010»
13 years 6 months ago
Boolean matching of function vectors with strengthened learning
Boolean matching for multiple-output functions determines whether two given (in)completely-specified function vectors can be identical to each other under permutation and/or negat...
Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang
TC
1998
13 years 8 months ago
Using Decision Diagrams to Design ULMs for FPGAs
—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possib...
Zeljko Zilic, Zvonko G. Vranesic