44 search results - page 6 / 9 » Functional netlists |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on th...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
FPL
2006
Springer
13 years 10 months ago
2006
Springer
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
GLVLSI
2000
IEEE
13 years 11 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...