138 search results - page 10 / 28 » Functional test generation for delay faults in combinational... |
DATE
2002
IEEE
14 years 19 days ago
2002
IEEE
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
ISQED
2003
IEEE
14 years 29 days ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
DFT
2002
IEEE
14 years 19 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...