138 search results - page 17 / 28 » Functional test generation for delay faults in combinational... |
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
ITC
1997
IEEE
13 years 12 months ago
1997
IEEE
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...
DSD
2007
IEEE
14 years 2 months ago
2007
IEEE
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
VTS
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
ASPDAC
1998
ACM
13 years 12 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...