138 search results - page 23 / 28 » Functional test generation for delay faults in combinational... |
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
ATS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
CAI
2004
Springer
13 years 7 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...