138 search results - page 27 / 28 » Functional test generation for delay faults in combinational... |
TCAD
2011
13 years 2 months ago
2011
—This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-oncapture (LOC) scheme followed by the one-hot LOC scheme for testing ...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
CONSTRAINTS
2007
13 years 7 months ago
2007
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...