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ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 3 days ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
ECCV
2000
Springer
16 years 4 months ago
Diffeomorphic Matching Problems in One Dimension: Designing and Minimizing Matching Functionals
This paper focuses on matching 1D structures by variational methods. We provide rigorous rules for the construction of the cost function, on the basis of an analysis of properties ...
Alain Trouvé, Laurent Younes
GECCO
2010
Springer
182views Optimization» more  GECCO 2010»
15 years 5 months ago
Benchmarking CMA-EGS on the BBOB 2010 noisy function testbed
This paper describes the implementation and the results for CMA-EGS on the BBOB 2010 noisy testbed. The CMAEGS is a hybrid strategy which combines elements from gradient search an...
Steffen Finck, Hans-Georg Beyer
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
15 years 8 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
15 years 6 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita