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COLOGNETWENTE
2009
13 years 9 months ago
Integer Programming with 2-Variable Equations and 1-Variable Inequalities
We present an efficient algorithm to find an optimal integer solution of a given system of 2-variable equalities and 1-variable inequalities with respect to a given linear objectiv...
Manuel Bodirsky, Gustav Nordh, Timo von Oertzen
ISVLSI
2003
IEEE
97views VLSI» more  ISVLSI 2003»
14 years 1 months ago
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
Andrew B. Kahng, Bao Liu
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
EUC
2006
Springer
13 years 11 months ago
On Multiprocessor Utility Accrual Real-Time Scheduling with Statistical Timing Assurances
We present the first Utility Accrual (or UA) real-time scheduling algorithm for multiprocessors, called gMUA. The algorithm considers an application model where real-time activiti...
Hyeonjoong Cho, Haisang Wu, Binoy Ravindran, E. Do...
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
14 years 2 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang