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ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
15 years 10 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 10 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
15 years 10 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
INFOCOM
2000
IEEE
15 years 8 months ago
Egress Admission Control
—Allocating resources for multimedia traffic flows with real-time performance requirements is an important challenge for future packet networks. However, in large-scale networks,...
Coskun Cetinkaya, Edward W. Knightly
EUROISI
2008
15 years 5 months ago
Homeland Security Data Mining Using Social Network Analysis
The tragic events of September 11th have caused drastic effects on many aspects of society. Academics in the fields of computational and information science have been called upon ...
Hsinchun Chen