171 search results - page 3 / 35 » Future Performance Challenges in Nanometer Design |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practi...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must b...
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...