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DAC
2002
ACM
14 years 11 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 4 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
IEEEPACT
2006
IEEE
14 years 3 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
ESCIENCE
2005
IEEE
14 years 3 months ago
Experiences with GRIA - Industrial Applications on a Web Services Grid
The GRIA project set out to make the Grid usable by industry. The GRIA middleware is based on Web Services, and designed to meet the needs of industry for security and business-to...
Mike Surridge, Steve Taylor, David De Roure, Ed Za...
HT
2005
ACM
14 years 3 months ago
Information visualization for an intrusion detection system
— Spatial hypertext was developed from studies of how humans deal with information overflow particularly in situations where data needed to be interpreted quickly. Intrusion det...
James Blustein, Ching-Lung Fu, Daniel L. Silver