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FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 4 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 3 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
FDL
2003
IEEE
14 years 4 months ago
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
Mauricio Ayala-Rincón, Ricardo P. Jacobi, C...
DAC
2006
ACM
14 years 5 months ago
Design in reliability for communication designs
Silicon design implementation has become increasingly complex with the deep submicron technologies such as 90nm and below. It is common to see multiple processor cores, several ty...
Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar
JIPS
2010
195views more  JIPS 2010»
13 years 5 months ago
Distributed and Scalable Intrusion Detection System Based on Agents and Intelligent Techniques
Abstract--The Internet explosion and the increase in crucial web applications such as ebanking and e-commerce, make essential the need for network security tools. One of such tools...
Aly M. El-Semary, Mostafa Gadal-Haqq M. Mostafa