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» Fuzzy logic in architectural design
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DAC
2006
ACM
14 years 12 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
EH
1999
IEEE
351views Hardware» more  EH 1999»
14 years 3 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
ICES
2001
Springer
105views Hardware» more  ICES 2001»
14 years 3 months ago
Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates
Abstract. Evolvable Hardware (EHW) has been proposed as a new method for designing systems for real-world applications. In this paper it is applied for evolving a prosthetic hand c...
Jim Torresen
RTAS
2009
IEEE
14 years 5 months ago
The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
Stanley Bak, Deepti K. Chivukula, Olugbemiga Adeku...
FPGA
1998
ACM
146views FPGA» more  FPGA 1998»
14 years 3 months ago
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...
Jason Cong, Yean-Yow Hwang