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FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
14 years 2 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
ET
2007
123views more  ET 2007»
13 years 11 months ago
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies introduce numero...
Tad Hogg, Greg Snider
FPT
2005
IEEE
134views Hardware» more  FPT 2005»
14 years 4 months ago
Post-Silicon Debug Using Programmable Logic Cores
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
Bradley R. Quinton, Steven J. E. Wilton
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
14 years 4 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
DAC
2008
ACM
15 years 4 days ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel