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DAC
2004
ACM
14 years 29 days ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
CAV
2004
Springer
99views Hardware» more  CAV 2004»
14 years 28 days ago
Range Allocation for Separation Logic
Abstract. Separation Logic consists of a Boolean combination of predicates of the form vi ≥ vj +c where c is a constant and vi, vj are variables of some ordered infinite type li...
Muralidhar Talupur, Nishant Sinha, Ofer Strichman,...
EUROPAR
2004
Springer
14 years 27 days ago
A Coarse-Grained Parallel Algorithm for Spanning Tree and Connected Components
Computing a spanning tree and the connected components of a graph are basic problems in Graph Theory and arise as subproblems in many applications. Dehne et al. present a BSP/CGM a...
Edson Norberto Cáceres, Frank K. H. A. Dehn...
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 25 days ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
CP
2003
Springer
14 years 22 days ago
Redundant Modeling for the QuasiGroup Completion Problem
Abstract. The Quasigroup Completion Problem (QCP) is a very challenging benchmark among combinatorial problems, and the focus of much recent interest in the area of constraint prog...
Iván Dotú, Alvaro del Val, Manuel Ce...