32 search results - page 4 / 7 » Gate Level Statistical Simulation Based on Parameterized Mod... |
ATS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
PATMOS
2007
Springer
14 years 1 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
VTC
2008
IEEE
14 years 1 months ago
2008
IEEE
— A dense urban cellular environment contains many different locations where a line-of-sight or specular signal component from the base station is present. The small scale fading...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...