694 search results - page 20 / 139 » Gate Sizing Using a Statistical Delay Model |
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clockless) control circuits. Because speed-independent circuits are hazard-free...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
MSWIM
2005
ACM
14 years 1 months ago
2005
ACM
The performance of mobile ad hoc networks can be influenced by numerous factors, including protocol design at every layer; parameter settings such as retransmission limits and ti...
ICCAD
1999
IEEE
14 years 14 hour ago
1999
IEEE
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...