694 search results - page 23 / 139 » Gate Sizing Using a Statistical Delay Model |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
GRID
2008
Springer
13 years 7 months ago
2008
Springer
The existence of good probabilistic models for the job arrival process and the delay components introduced at different stages of job processing in a Grid environment is important ...
VLSI
2005
Springer
14 years 1 months ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...