694 search results - page 29 / 139 » Gate Sizing Using a Statistical Delay Model |
TMC
2012
11 years 11 months ago
2012
—Characterizing the performance of ad hoc networks is one of the most intricate open challenges; conventional ideas based on information-theoretic techniques and inequalities hav...
MEMOCODE
2007
IEEE
14 years 3 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
DAC
2004
ACM
14 years 21 days ago
2004
ACM
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
GLOBECOM
2008
IEEE
14 years 3 months ago
2008
IEEE
—In this paper we propose a model to compute an upper bound for the maximum network size in mobile ad-hoc networks. Our model is based on the foundation that for a unicast route ...
BMCBI
2008
13 years 9 months ago
2008
Background: Choosing the appropriate sample size is an important step in the design of a microarray experiment, and recently methods have been proposed that estimate sample sizes ...