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» Gate Sizing Using a Statistical Delay Model
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MOBIHOC
2008
ACM
14 years 8 months ago
Routing performance analysis of human-driven delay tolerant networks using the truncated levy walk model
The routing performance of delay tolerant networks (DTN) is highly correlated with the distribution of inter-contact times (ICT), the time period between two successive contacts o...
Seongik Hong, Injong Rhee, Seong Joon Kim, Kyungha...
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 9 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 2 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 1 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
ICCD
2007
IEEE
120views Hardware» more  ICCD 2007»
14 years 5 months ago
Statistical timing analysis using Kernel smoothing
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...