694 search results - page 39 / 139 » Gate Sizing Using a Statistical Delay Model |
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
LCN
2007
IEEE
14 years 3 months ago
2007
IEEE
— An approach is presented to capture and model Internet end-to-end packet delay behavior using ARMA and ARIMA models. Autocorrelation (ACF) and Partial Autocorrelation (PACF) fu...
PAMI
2007
13 years 8 months ago
2007
As biometric authentication systems become more prevalent, it is becoming increasingly important to evaluate their performance. The current paper introduces a novel statistical me...
VTS
1996
IEEE
14 years 1 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...