694 search results - page 40 / 139 » Gate Sizing Using a Statistical Delay Model |
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of ...
TCAD
1998
13 years 8 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ICIP
2002
IEEE
14 years 10 months ago
2002
IEEE
This paper presents an extensive statistical study and analysis of the effects of channel delays in the current (best-effort) Internet on underflow events in MPEG-4 video streamin...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...