694 search results - page 47 / 139 » Gate Sizing Using a Statistical Delay Model |
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
IROS
2009
IEEE
14 years 3 months ago
2009
IEEE
— In this paper we describe a method for bridging internet time delays in a teleoperation scenario. In the scenario, the sizes of the time delays is not only stochastic, but it i...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
LREC
2008
13 years 10 months ago
2008
In current phrase-based Statistical Machine Translation systems, more training data is generally better than less. However, a larger data set eventually introduces a larger model ...